1. Field of the Invention
The present invention relates to a fabrication method an integrated circuit. More particularly, the present invention relates to a method for fabricating a shallow trench isolation (STI).
2. Description of Related Art
A complete integrated circuit is normally formed with many transistor devices. In order to prevent a circuit shorting between these neighboring transistors, isolated region are formed between the neighboring transistors to isolate the transistors. A typical device isolation region is formed in densely packed semiconductor circuits, for example, between neighboring field effect transistors (FET) in a memory device to reduce the charge leakage of the field effect transistors.
Shallow trench isolation is a trench formed in a semiconductor substrate by employing the technique of anisotropic etching followed by filling the trench with an oxide layer to form an isolation region. Since the isolation region, formed by the shallow trench isolation method, is scalable. Further, the drawback of the bird""s beak encroachment in the conventional LOCOS isolation technique is prevented. Therefore, STI is a more favorable isolation technique for the sub-micron metal oxide semiconductor processing.
FIGS. 1A to 1D illustrate the process flow in fabricating a shallow trench isolation region according to the prior art.
Referring to FIG. 1A, the conventional fabrication method for a shallow trench isolation region includes forming a hard mask layer 12 on a substrate. A patterned photoresist layer is then formed on the hard mask layer 12. However, during the patterning of the photoresist layer 14, an interaction is present between the photoresist layer 14 and the hard mask layer 12. The photoresist layer 14 at where the trench is going to be formed can not be cleaned completely. Photoresist residue 16 is thus remained on the hard mask layer 12.
Thereafter, as shown in FIG. 1B, an etching is performed to pattern the hard mask layer 12 using the photoresist layer 14 as an etching mask. Further using the photoresist layer 14 and the hard mask layer 12 as an etching mask, another etching is performed to pattern the substrate 10 to form a trench 18 in the substrate 10. However, in the previous process steps, residue 16 is remained on the surface of the hard mask layer 12. Therefore, during the patterning of the hard mask layer 12 and the substrate 10, the residues 16 needs to be etched completely before the etching of the substrate 10 underneath the residues 16. The presence and absence of resides 16 induce a non-uniform etch rate, and an island defect 20 is thus formed in the trench 18.
Referring to FIG. 1C, the photoresist layer 14 is removed, followed by filling an insulation layer 22 in the trench 18. Thereafter, as shown in FIG. 1D, the mask layer 12 is removed and a shallow trench isolation region is formed. The island defect 20, however, is a silicon material. The presence of the silicon type island defect 20 in the shallow trench isolation region affects not only the isolation capability of the isolation region. If the island defect 20 is formed near the border of the trench 18, a current leakage of the device is easily resulted.
Accordingly, the present invention provides a fabrication method for a shallow trench isolation region, wherein an island shaped defect is precluded from forming in the shallow trench isolation region.
The present invention also provides a fabrication method for a shallow trench isolation region, wherein the shallow trench isolation region can effectively isolate the neighboring devices to prevent a current leakage of the device.
The present invention provides a fabrication method for a shallow trench isolation region, wherein a hard mask layer is formed over a substrate. An ion bombardment process is performed on the surface of the hard mask layer. The plasma gas used in the ion bombardment process includes nitrous oxide (N2O), oxygen (O2), nitrogen (N2) or argon (Ar). The ion bombardment process is performed at a temperature of about 200 degrees Celsius to 500 degrees Celsius, under a pressure of about 3 mTorr to 2 Torr and with a power of 100 W to 1000 W. Further, the gas flow rate of the ion bombardment process is about 150 sccm to about 3000 sccm. A photoresist layer is then formed on the ion-bombarded hard mask layer, followed by an exposure process and a development process to pattern the hard mask layer, wherein the area where the trench is going to be formed is exposed. Since the hard mask layer is already treated with the ion bombardment process, the exposed photoresist layer can be completely removed during the exposure process and no residue remains on the hard mask layer. After this, using the photorsist layer as an etching mask, the hard mask layer is patterned. Further using the photoresist layer and the hard mask layer as an etching mask, the substrate is patterned to form a trench in the substrate. Thereafter, the photoresist layer is removed, followed by filling the trench with an insulation layer. The hard mask is further removed to complete a formation of a shallow trench isolation structure.
The fabrication method for a shallow trench isolation region of the present invention includes forming a hard mask layer over a substrate. A thin material layer, e.g., a thin oxide layer, is then formed on the surface of the hard mask layer. A photoresist layer is further formed on the thin oxide layer. An exposure and development process is then performed to pattern the photoresist layer, wherein the region where the trench is going to be formed is exposed. Since the interaction between the thin oxide layer and the photoresist layer is weaker, the exposed photoresist layer can be completely cleaned during the development of the photoresist layer. No residue is remaining on the thin oxide layer. Then, using the photresist layer as an etching mask, the hard mask layer is patterned. Further using the photoresis layer and the hard mask layer as an etching mask, the substrate is patterned to form a trench in the substrate. In other aspect of the present invention, the photoresist layer can be first removed, followed by patterning the substrate to form a trench in the substrate, using the hard mask layer as an etching mask. Thereafter, the photoresist further removed to complete a formation of a shallow trench isolation region.
The present invention provides a method for fabricating a shallow trench isolation region, wherein an ion bombardment process is performed on the surface of the hard mask layer to prevent the photoresist residue remaining and to further prevent the formation of an island defect in the shallow trench isolation region.
The present invention provides a fabrication method for a shallow trench isolation region, wherein a thin material layer is formed on the surface of the hard mask layer to prevent the photoresist residue remaining and to further prevent the formation of an island defect in the shallow trench isolation region.
The fabrication method for a shallow trench isolation region of the present invention prevents the formation of an island defect to raise the isolation effect of the shallow trench isolation region and to effectively prevent a current leakage.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.